1. Field of the Invention
The present invention relates to an apparatus and method for verifying timing between signals.
2. Description of the Related Art
In a logic circuit, a common signal is used for data latch. As the common signals, there are timing signals such as a clock signal, a set signal, and a reset signal. The clock signal undergoes physical influence from a lot of logic cells in the logic circuit while being propagated in the circuit so that the waveform is made dull. A data signal is delayed due to logical cells and wiring line capacitance until the data signal reaches a target logic cell while being propagated in the logic circuit after being inputted from an input terminal of the logic circuit. The data signal is generally latched by a latch circuit at a rising edge or falling edge of the clock signal. For example, when a data signal whose logical value changes immediately before a latch timing should be latched by a latch circuit, the latch condition is the most severe. Under such a condition, when the slew of signal waveform is too large, it is not possible to correctly latch the data signal even if the data signal arrives.
A technique for the timing verification of the difference between the arrival time of the data signal and the arrival time of the clock signal is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-179888). For the technique, it is important to verify the difference between a waveform with slew and another waveform with no slew. If the arrival time of the clock signal and the arrival time of the data signal are the same even if the signals are delayed, the delay does not become hindrance at all for the operation of a computer. However, if the signal waveform is dully changed so that the signal does not over a threshold voltage, a logic cell operates erroneously.
FIG. 1 shows the relation of a normal clock signal with no slew and a clock signal with slew. The solid line waveform shows the ideal waveform with no slew of the normal clock signal. The rising edge or falling edge of the normal signal is used as the timing at which the data signal is latched. The dotted line waveform shows a signal waveform with slew of the normal clock signal. The threshold voltage is shown by one chain line. When the signal waveform of the clock signal exceeds the threshold voltage Vth at the point P, the data signal is latched. However, when the clock signal passes away a desired latch timing, in other words, the timing that the data signal should be latched is missed, the data signal cannot be correctly latched by the latch. The delay time between the ideal rising timing of the clock signal and the actual rising timing of the clock signal (point P) is defined as the slew time of the clock signal.
FIG. 2 shows a conventional simulator, which is used for circuit design of a logic circuit in consideration of the slews of the signals. As shown in FIG. 2, the conventional simulator is composed of a library 105, which stores slews or slews of signals for every unit logic cell. The slews are represented by a 2-variable function of a capacitance C and a resistance R. When a reference value of a threshold value is set, the latch times for the signal waveforms with the slews A, B and C shown in FIG. 4 are determined to be the times t1, t2 and t3, respectively. Thus, the library 105 stores the relation between a set of the capacitance Cj and the resistance Rk and the delay time until the signal waveform exceeds the threshold value. Also, FIG. 3 shows the maximum slew of the signal waveform permissible in the circuit is stored in the library 105 as the worst value. The worst value has no dependence on frequency.
As shown in FIG. 2, the conventional simulator is composed of a net list 101, a delay calculator 102, a slew data file 103, and a determining unit 104. The slew of the signal waveform is calculated using a well known equation for the slew of a signal waveform. When the calculated slew of the signal waveform is larger at a logic cell than the worst value stored in the library 105, a circuit using the logic cell is determined to operate erroneously. The conventional simulator carries out an error determination based on the peculiar worst value of the slew for each logic cell without consideration of a frequency of the clock signal.
Therefore, an object of the present invention is to provide a system and method for verifying timing between signals under the consideration of the delay and slew of the signals.
In an aspect of the present invention, a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, is attained by (a) determining first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal, and a second delay data, a second waveform slew data and second signal data indicating a frequency, duty ratio and jitter of the second signal to the object logic cell; by (b) calculating in time, a first portion of a first waveform of the first signal at the object logic cell based on the first delay data, the first waveform slew data and the first signal data; by (c) calculating in time, a second portion of a second waveform of the second signal at the object logic cell based on the second delay data, the second waveform slew data and the second signal data; and by (d) evaluating whether the first portion of the first waveform overlaps the second portion of the second waveform.
Here, the (a) determination may be attained by (e) providing first to third tables, wherein the first table stores delay data associated with signals in the logic circuit, the second table stores waveform slew data associated with the signals in the logic circuit, and the third table previously stores signal data of a frequency, duty ratio and jitter associated with at least one of the signals in the logic circuit; and by (f) referring to the first table the based on the first signal and the second signal to determine the first delay data of the first signal and the second delay data of the second signal from the delay data stored in the first table, respectively, to the second table the based on the first signal and the second signal to determine the first waveform slew data of the first signal and the second waveform slew data of the second signal from the waveform slew data stored in the second table, respectively, and to the third table the based on the first and second signals to determine the first and second signal data from the signal data stored in the third table, respectively.
Also, the (a) determination may be additionally attained by (g) providing a fourth table storing net list data indicative of the logic circuit by signal paths and the logic cells; by (h) previously calculating the delay data and the waveform slew data for each of the signal paths and the plurality of logic cells based on the net list data to store in the first and second tables, respectively.
Also, the (f) referring may be attained by (i) tracing a first transfer path of the first signal from the first external input terminal to the object logic cell using the net list data; by (j) tracing a second transfer path of the second signal from a second external input terminal to the object logic cell using the net list data; by (k) calculating the first delay data of the first signal based on the delay data stored in the first table, the first signal data and the first transfer path; by (l) calculating the first waveform slew data of the first signal based on the waveform slew data stored in the second table, the first signal data and the first transfer path; by (m) calculating the second delay data of the second signal based on the delay data stored in the first table, the second signal data and the second transfer path; and by (n) calculating the second waveform slew data of the second signal based on the waveform slew data stored in the second table and the second transfer path.
Also, the (b) calculation may be attained by calculating a first minimum falling time, a first maximum falling time, a first minimum rising time, and a first maximum rising time for the first portion of the first signal waveform of the first signal at the object logic cell based on the first delay data, the first slew data and the first signal data. The (c) calculation may be attained by calculating a second minimum falling time, a second maximum falling time, a second minimum rising time, and a second maximum rising time for the second portion of the second waveform of the second signal at the object logic cell based on the second slew data.
In this case, the first portion of the first waveform may be defined as (the first minimum falling time)xe2x88x92(the first maximum rising time), the second portion of the second waveform may be defined as (the second minimum falling time)xe2x88x92(the second maximum rising time). Also, the first portion of the first waveform may be defined as (the first minimum falling time)xe2x88x92(the first maximum rising time), and the second portion of the second waveform may be defined as (the second minimum rising time)xe2x88x92(the second maximum falling time). Also, the first portion of the first waveform may be defined as (the first minimum rising time)xe2x88x92(the first maximum falling time), and the second portion of the second waveform may be defined as (the second minimum falling time)xe2x88x92(the second maximum rising time). Otherwise, the first portion of the first waveform may be defined as (the first minimum rising time)xe2x88x92(the first maximum falling time), and the second portion of the second waveform may be defined as (the second minimum rising time)xe2x88x92(the second maximum falling time).
In order to achieve another aspect of the present invention, a system for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, includes first to third tables and an evaluating unit. The first table stores delay data associated with signals in the logic circuit. The second table stores waveform slew data associated with the signals in the logic circuit. The third table previously stores signal data of a frequency, duty ratio and jitter associated with at least one of the signals in the logic circuit. The evaluating unit refers to the first table based on the first signal and the second signal to determine first delay data of the first signal and the second delay data of the second signal from a first external input terminal to the object logic cell from the delay data stored in the first table, respectively, to the second table the based on the first signal and the second signal to determine the first waveform slew data of the first signal to the object logic cell and the second waveform slew data of the second signal to the object logic cell from the waveform slew data stored in the second table, respectively, and to the third table based on the first and second signals to determine the first and second signal data from the signal data stored in the third table, respectively. Also, the evaluating unit calculates in time, a first portion of a first waveform of the first signal at the object logic cell based on the first delay data, the first waveform slew data and the first signal data. Further, the evaluating unit calculates in time, a second portion of a second waveform of the second signal at the object logic cell based on the second delay data, the second waveform slew data and the second signal data, and evaluates whether the first portion of the first waveform overlaps the second portion of the second waveform.
In this case, the system may further include a fourth table which stores net list data indicative of the logic circuit by signal paths and the logic cells. The evaluating unit previously calculates the delay data and the waveform slew data for each of the signal paths and the plurality of logic cells based on the net list data to store in the first and second tables, respectively.
Also, the evaluating unit may:
trace a first transfer path of the first signal from the first external input terminal to the object logic cell using the net list data,
trace a second transfer path of the second signal from a second external input terminal to the object logic cell using the net list data;
calculates the first delay data of the first signal based on the delay data stored in the first table, the first signal data and the first transfer path;
calculates the first waveform slew data of the first signal based on the waveform slew data stored in the second table, the first signal data and the first transfer path;
calculates the second delay data of the second signal based on the delay data stored in the first table, the second signal data and the second transfer path; and
calculates the second waveform slew data of the second signal based on the second delay data, the waveform slew data stored in the second table and second transfer path.
Also, the evaluating unit may:
calculate a first minimum falling time, a first maximum falling time, a first minimum rising time, and a first maximum rising time for the first portion of the first signal waveform of the first signal at the object logic cell based on the first delay data, the first slew data and the first signal data, and
calculate a second minimum falling time, a second maximum falling time, a second minimum rising time, and a second maximum rising time for the second portion of the second waveform of the second signal at the object logic cell based on the second slew data.
In this case, the evaluating unit whether the first portion of the first waveform overlaps the second portion of the second waveform in time, based on one of (the first minimum falling time)xe2x88x92(the first maximum rising time) and (the first maximum rising time)xe2x88x92(the first minimum falling time) and one of (the second minimum falling time)xe2x88x92(the second maximum rising time) and (the second maximum rising time)xe2x88x92(the second minimum falling time).
In order to achieve still another aspect of the present invention, a recording medium is provided in which a program is recorded for a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell. The method is attained by (a) determining first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal, and a second waveform slew data and second signal data indicating a frequency, duty ratio and jitter of the second signal to the object logic cell; by (b) calculating in time, a first portion of a first waveform of the first signal at the object logic cell based on the first delay data, the first waveform slew data and the first signal data; by (c) calculating in time, a second portion of a second waveform of the second signal at the object logic cell based on the second delay data, the second waveform slew data and the second signal data; and by (d) evaluating whether the first portion of the first waveform overlaps the second portion of the second waveform.